Semiconductors have advanced to be highly integrated and to operate at high speed and low voltage. There has been a great deal of research and development in connection with the reduction of the design rule and adaptation of new materials and processes. For example, some efforts have been directed to the utilization of copper wiring and low-k material to reduce the resistance X capacitance (RC) delay. Copper wiring has a low resistivity in comparison to conventional aluminum wiring and, as a result, reduces delay times and provides relatively high electro-migration (EM) and stress migration (SM) resistances, which results in advantageous electrical performance. Low-k materials such as diamond like carbon (DLC), carbon doped oxide (CDO) and the like are being considered for use in fabricating copper wiring in 90 nm or narrower line width process.
The copper wiring process differs from the conventional aluminum wiring process in several respects. First, in the aluminum wiring process, the aluminum wiring is formed by depositing an aluminum layer and carrying out a photolithography process and a reactive ion etching process. Sequentially, a dielectric layer is deposited to insulate the wiring from each other, and then the dielectric layer is planarized using chemical mechanical polishing to remove the topography on the surface of the dielectric layer.
Next, a via hole is formed to couple upper and lower wiring therethrough. The via hole is filled by depositing a metal layer such as a tungsten layer, and then the tungsten layer is planarized through a chemical mechanical polishing process.
Even though aluminum wiring can be easily patterned by depositing it and using a dry etch technique, it is relatively unlikely to be used because of its high resistivity. Accordingly, there have been efforts to form the wiring out of copper, which has a resistivity lower than that of the aluminum.
However, it is not easy to pattern the copper using dry etching and, as a result, the damascene process has been developed to form copper wiring. In the damascene process, after depositing the dielectric layer, a trench is formed using photolithography and a reactive ion etching process, and then the trench is filled with the copper by carrying out an electrochemical plating process. During the course of the electrochemical plating process, a barrier metal layer formed out of Ta/TaN and a Cu seed are typically required.
A dual damascene process forms the trench and the via hole at the same time and, as a result, is used for most of the copper wiring processes. In such copper wiring processes, the electrochemical plating process has characteristics different from the conventional deposition process. The conventional deposition process is characterized in that the copper is conformably deposited according to the formation of the lower pattern.
However, a case of the electrochemical plating the above-mentioned copper seed is needed for deposition of a hump in which a trench region has a step higher than non-trench regions also occurs. The hump characteristic is opposite to the characteristic shown in a chemical vapor deposition process, and it occurs by relatively increasing the electric charge at a dense pattern region. As the stepped height due to the hump increases, the amount of material that must be removed in the copper planarization process increases. The need to remove an increased amount of material increases defects such as dishing caused by non-uniformity in the wafer. Also, the electrochemical plating process is problematic in a mass production environment because of difficulties in controlling impurities and disposing of the wastewater. In addition, U.S. Pat. Nos. 4,855,016, 5,795,829, and 6,291,336 disclose methods for fabricating the metal wiring using aluminum-copper alloys.